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Low Vccmin fault-tolerant cache with highly predictable performance
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Carretero Casado, Javier Sebastián |
dc.contributor.author | Chaparro Valero, Pedro Alonso |
dc.contributor.author | Vera Rivera, Francisco Javier |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2010-06-29T09:59:53Z |
dc.date.available | 2010-06-29T09:59:53Z |
dc.date.created | 2009 |
dc.date.issued | 2009 |
dc.identifier.citation | Abella, J. [et al.]. Low Vccmin fault-tolerant cache with highly predictable performance. A: IEEE/ACM International Symposium on Microarchitecture. "42th. IEEE/ACM International Symposium on Microarchitecture". New York, DC: IEEE Press. Institute of Electrical and Electronics Engineers, 2009, p. 111-121. |
dc.identifier.uri | http://hdl.handle.net/2117/7879 |
dc.description.abstract | Transistors per area unit double in every new technology node. However, the electric field density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace with new technology nodes to prevent excessive degradation and keep power demand within reasonable limits. Unfortunately, low Vcc operation exacerbates the effect of variations and decreases noise and stability margins, increasing the likelihood of errors in SRAM memories such as caches. Those errors translate into performance loss and performance variation across different cores, which is especially undesirable in a multi-core processor. This paper presents (i) a novel scheme to tolerate high faulty bit rates in caches by disabling only faulty subblocks, (ii) a dynamic address remapping scheme to reduce performance variation across different cores, which is key for performance predictability, and (iii) a comparison with state-of-the-art techniques for faulty bit tolerance in caches. Results for some typical first level data cache configurations show 15% average performance increase and standard deviation reduction from 3.13% down to 0.55% when compared to cache line disabling schemes. |
dc.format.extent | 11 p. |
dc.language.iso | eng |
dc.publisher | IEEE Press. Institute of Electrical and Electronics Engineers |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors |
dc.subject.lcsh | Cache memory |
dc.title | Low Vccmin fault-tolerant cache with highly predictable performance |
dc.type | Conference report |
dc.subject.lemac | Memòria cau |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 2568937 |
dc.description.version | Postprint (published version) |
local.citation.author | Abella, J.; Carretero, J.; Chaparro, P.; Vera, F.; González, A. |
local.citation.contributor | IEEE/ACM International Symposium on Microarchitecture |
local.citation.pubplace | New York, DC |
local.citation.publicationName | 42th. IEEE/ACM International Symposium on Microarchitecture |
local.citation.startingPage | 111 |
local.citation.endingPage | 121 |