Mostra el registre d'ítem simple
Prebond testing of weak defects in TSVs
dc.contributor.author | Arumi Delgado, Daniel |
dc.contributor.author | Rodríguez Montañés, Rosa |
dc.contributor.author | Figueras Pàmies, Joan |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2015-10-29T08:56:26Z |
dc.date.issued | 2015-08-07 |
dc.identifier.citation | Arumi, D., Rodriguez, R., Figueras, J. Prebond testing of weak defects in TSVs. "IEEE transactions on very large scale integration (VLSI) systems", 07 Agost 2015, vol. PP, núm. 99, p. 31-36. |
dc.identifier.issn | 1063-8210 |
dc.identifier.uri | http://hdl.handle.net/2117/78462 |
dc.description.abstract | Through-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process to prevent stacking yield loss. Thus, the development of effective prebond testing techniques becomes of great importance. In this direction, recent research effort has been devoted to the development of two main prebond techniques: 1) prebond probing and 2) built-in self-test (BIST) techniques. The prebond probing poses economic and technological challenges, whereas current BIST proposals have disadvantages for certain solutions. Hence, there is still a need for an effective methodology in terms of fault coverage, area overhead, and test time. This paper proposes a BIST technique based on a simple unbalanced circuit comparing the behavior of two TSVs. Electrical simulation results show the viability of the proposal to detect weak defects, i.e., resistive opens and resistive bridges, adding reasonable area overhead in a short-test application time. Furthermore, an experimental design is built on a 65-nm technology, where resistive open defects are intentionally injected. Automated test equipment measurements confirm the simulation results |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Stability |
dc.subject.lcsh | Electric inverters |
dc.subject.lcsh | Integrated circuits |
dc.subject.other | Built-in self-test |
dc.subject.other | Circuit faults |
dc.subject.other | Circuit stability |
dc.subject.other | Inverters |
dc.subject.other | Stability analysis |
dc.subject.other | Through-silicon vias |
dc.subject.other | Built-in self-test (BIST) |
dc.subject.other | design for testability |
dc.subject.other | integrated circuit (IC) testing |
dc.title | Prebond testing of weak defects in TSVs |
dc.type | Article |
dc.subject.lemac | Circuits integrats |
dc.contributor.group | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.identifier.doi | 10.1109/TVLSI.2015.2448594 |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7182374 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 16843059 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Arumi, D.; Rodriguez, R.; Figueras, J. |
local.citation.publicationName | IEEE transactions on very large scale integration (VLSI) systems |
local.citation.volume | PP |
local.citation.number | 99 |
local.citation.startingPage | 31 |
local.citation.endingPage | 36 |
Fitxers d'aquest items
Aquest ítem apareix a les col·leccions següents
-
Articles de revista [1.727]
-
Articles de revista [74]