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dc.contributor.authorHussain, Tassadaq
dc.contributor.authorHaider, Amna
dc.contributor.authorGursal, Shakaib A.
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2015-10-27T16:29:04Z
dc.date.available2017-10-27T00:30:21Z
dc.date.issued2015-01
dc.identifier.citationHussain, T., Haider, A., Gursal, S., Ayguade, E. AMC: Advanced Multi-accelerator Controller. "Parallel computing", Gener 2015, vol. 41, p. 14-30.
dc.identifier.issn0167-8191
dc.identifier.urihttp://hdl.handle.net/2117/78376
dc.description.abstractThe rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS multi-accelerator system requires a microprocessor (master core) that manages memory and schedules accelerators. In a real environment, such HLS multi-accelerator systems do not give a perfect performance due to memory bandwidth issues. Thus, a system demands a memory manager and a scheduler that improves performance by managing and scheduling the multi-accelerator’s memory access patterns efficiently. In this article, we propose the integration of an intelligent memory system and efficient scheduler in the HLS-based multi-accelerator environment called Advanced Multi-accelerator Controller (AMC). The AMC system is evaluated with memory intensive accelerators, High Performance Computing (HPC) applications and implemented and tested on a Xilinx Virtex-5 ML505 evaluation FPGA board. The performance of the system is compared against the microprocessor-based systems that have been integrated with the operating system. Results show that the AMC based HLS multi-accelerator system achieves 10.4x and 7x of speedup compared to the MicroBlaze and Intel Core based HLS multi-accelerator systems.
dc.format.extent17 p.
dc.language.isoeng
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshHigh performance computing
dc.subject.lcshField programmable gate arrays
dc.subject.otherHPC
dc.subject.otherFPGA
dc.subject.otherMaster core
dc.subject.otherHLS
dc.titleAMC: Advanced Multi-accelerator Controller
dc.typeArticle
dc.subject.lemacCàlcul intensiu (Informàtica)
dc.subject.lemacMatrius de portes programables per l'usuari
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1016/j.parco.2014.10.003
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://www.sciencedirect.com/science/article/pii/S0167819114001264
dc.rights.accessOpen Access
local.identifier.drac15625999
dc.description.versionPostprint (author’s final draft)
local.citation.authorHussain, T.; Haider, A.; Gursal, S.; Ayguade, E.
local.citation.publicationNameParallel computing
local.citation.volume41
local.citation.startingPage14
local.citation.endingPage30


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