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dc.contributorMoreto Planas, Miquel
dc.contributorValero Cortés, Mateo
dc.contributorCasas Guix, Marc
dc.contributor.authorDimic, Vladimir
dc.date.accessioned2015-10-20T15:24:35Z
dc.date.issued2015-07-09
dc.identifier.urihttp://hdl.handle.net/2117/77989
dc.language.isoeng
dc.publisherUniversitat Politècnica de Catalunya
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMemory hierarchy (Computer science)
dc.subject.othercache
dc.subject.otherarquitectura de computadors
dc.subject.otherdisseny del processador
dc.subject.otherruntime
dc.subject.othersistema operatiu
dc.subject.othermodel de programació basat en tasques
dc.subject.otherprocessor cache
dc.subject.othercomputer architecture
dc.subject.otherprocessor design
dc.subject.otherruntime
dc.subject.otheroperating system
dc.subject.othertask-based programming model
dc.titleRuntime assisted cache memory optimizations
dc.typeMaster thesis
dc.subject.lemacJerarquia de memòria (Informàtica)
dc.identifier.slug108924
dc.rights.accessRestricted access - confidentiality agreement
dc.date.lift10000-01-01
dc.date.updated2015-07-11T04:00:37Z
dc.audience.educationlevelMàster
dc.audience.mediatorFacultat d'Informàtica de Barcelona


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