Resistive open defect characteritzation in 3D 6T SRAM memories

Abstract

The relentless decrease in feature size and the increase of density requirements in Integrated Circuit (IC) manufacturing arise new challenges that must be overcome. One of the most promising alternatives is three-dimensional integrated circuits (3D ICs). Several possibilities have been presented, but one of the clearest options is based on the use of Though-Silicon Vias (TSV) connections. The benefits and disadvantages that TSV inclusion adds to design need further studies. The implementation of these vertical vias can affect the general performance of circuit and thus changing verification strategies or testing processes. In this paper, the electrical effect of open defects affecting TSVs in a 3D SRAM module is presented. Analytical expressions are presented to provide designers a tool to improve circuit features and help them in the analysis of how TSV implementation can affect a SRAM array design