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dc.contributor.authorRodríguez Montañés, Rosa
dc.contributor.authorArumi Delgado, Daniel
dc.contributor.authorFigueras Pàmies, Joan
dc.contributor.authorEichenberger, Stefan
dc.contributor.authorHora, Camelia
dc.contributor.authorKruseman, Bram
dc.contributor.authorLousberg, M.
dc.contributor.authorMajhi, A.K.
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Disseny i Programació de Sistemes Electrònics
dc.date.accessioned2010-06-18T14:31:47Z
dc.date.available2010-06-18T14:31:47Z
dc.date.created2007-05-31
dc.date.issued2007-05-31
dc.identifier.citationRodríguez, R. [et al.]. Diagnosis of full open defects in interconnecting lines. A: IEEE VLSI Test Symposium. "25th IEEE VLSI Test Symposium". Berkeley: IEEE, 2007, p. 1-6.
dc.identifier.isbn0-7695-2812-0
dc.identifier.urihttp://hdl.handle.net/2117/7733
dc.descriptionBest Paper Award al millor article del congrés IEEE VLSI Test Symposium 2007
dc.description.abstractA proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherIEEE
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subject.lcshMetal oxide semiconductors, Complementary
dc.subject.lcshIntegrated circuits
dc.titleDiagnosis of full open defects in interconnecting lines
dc.typeConference report
dc.subject.lemacMetall-òxid-semiconductors complementaris
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.description.awardwinningAward-winning
dc.rights.accessOpen Access
local.identifier.drac2463423
dc.description.versionPostprint (published version)
local.citation.authorRodríguez, R.; Arumi, D.; Figueras, J.; Eichenberger, S.; Hora, C.; Kruseman, B.; Lousberg, M.; Majhi, A.K.
local.citation.contributorIEEE VLSI Test Symposium
local.citation.pubplaceBerkeley
local.citation.publicationName25th IEEE VLSI Test Symposium
local.citation.startingPage1
local.citation.endingPage6


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