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Diagnosis of full open defects in interconnecting linesAward-winning

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Rodríguez Montañés, RosaMés informacióMés informacióMés informació
Arumi Delgado, DanielMés informacióMés informacióMés informació
Figueras Pàmies, JoanMés informació
Eichenberger, Stefan
Hora, Camelia
Kruseman, Bram
Lousberg, M.
Majhi, A.K.
Document typeConference report
Defense date2007-05-31
PublisherIEEE
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
Abstract
A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.
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Best Paper Award al millor article del congrés IEEE VLSI Test Symposium 2007
CitationRodríguez, R. [et al.]. Diagnosis of full open defects in interconnecting lines. A: IEEE VLSI Test Symposium. "25th IEEE VLSI Test Symposium". Berkeley: IEEE, 2007, p. 1-6. 
Award-winningAward-winning
URIhttp://hdl.handle.net/2117/7733
ISBN0-7695-2812-0
Collections
  • Departament de Disseny i Programació de Sistemes Electrònics (fins octubre 2015) - Ponències/Comunicacions de congressos [36]
  • QINE - Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades - Ponències/Comunicacions de congressos [60]
  • QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat - Ponències/Comunicacions de congressos [78]
  • Departament d'Enginyeria Electrònica - Ponències/Comunicacions de congressos [1.583]
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