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dc.contributor.authorArumi Delgado, Daniel
dc.contributor.authorRodríguez Montañés, Rosa
dc.contributor.authorFigueras Pàmies, Joan
dc.contributor.authorEichenberger, Stefan
dc.contributor.authorHora, C.
dc.contributor.authorKruseman, Bram
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Disseny i Programació de Sistemes Electrònics
dc.identifier.citationArumi, D. [et al.]. Diagnosis of full open defects in interconnect lines with fan-out. A: EEE European Test Symposium. "15th European Test Symposium". Praga: IEEE, 2010, p. 233-238.
dc.description.abstractThe development of accurate diagnosis methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes a key factor. Widely used interconnect full open diagnosis procedures are based on the assumption that neighbouring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, when the influence of transistor capacitances becomes important. This work presents a diagnosis methodology for interconnect full open defects where the impact of transistor parasitic capacitances is included. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behaviour. Diagnosis results for real defective devices from different technology nodes are presented.
dc.format.extent6 p.
dc.publisherIEEE Press. Institute of Electrical and Electronics Engineers
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subject.lcshMetal oxide semiconductors, Complementary
dc.subject.lcshIntegrated circuits
dc.titleDiagnosis of full open defects in interconnect lines with fan-out
dc.typeConference report
dc.subject.lemacMetall-òxid-semiconductors complementaris
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
local.citation.authorArumi, D.; Rodríguez, R.; Figueras, J.; Eichenberger, S.; Hora, C.; Kruseman, B.
local.citation.contributorEEE European Test Symposium
local.citation.publicationName15th European Test Symposium

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