VSR sort: a novel vectorised sorting algorithm and architecture extensions for future microprocessors
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
Sorting is a widely studied problem in computer science and an elementary building block in many of its subfields. There are several known techniques to vectorise and accelerate a handful of sorting algorithms by using single instruction-multiple data (SIMD) instructions. It is expected that the widths and capabilities of SIMD support will improve dramatically in future microprocessor generations and it is not yet clear whether or not these sorting algorithms will be suitable or optimal when executed on them. This work extrapolates the level of SIMD support in future microprocessors and evaluates these algorithms using a simulation framework. The scalability, strengths and weaknesses of each algorithm are experimentally derived. We then propose VSR sort, our own novel vectorised non-comparative sorting algorithm based on radix sort. To facilitate the execution of this algorithm we define two new SIMD instructions and propose a complementary hardware structure for their execution. Our results show that VSR sort has maximum speedups between 14.9x and 20.6x over a scalar baseline and an average speedup of 3.4x over the next-best vectorised sorting algorithm.
CitationHayes, T., Palomar, O., Unsal, O., Cristal, A., Valero, M. VSR sort: a novel vectorised sorting algorithm and architecture extensions for future microprocessors. A: International Symposium on High-Performance Computer Architecture. "2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA 2015): Burlingame, California, USA: 7-11 February 2015". San Francisco Bay Area, California: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 26-38.
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