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dc.contributor.authorAcosta Ojeda, Carmelo Alexis
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-04-06T12:22:41Z
dc.date.available2010-04-06T12:22:41Z
dc.date.created2009
dc.date.issued2009
dc.identifier.citationAcosta, C. A. [et al.]. Thread to core assignment in SMT on-chip multiprocessors. "International symposium on computer architecture. Proceedings", 2009, p. 67-74.
dc.identifier.issn1063-6897
dc.identifier.urihttp://hdl.handle.net/2117/6860
dc.description.abstractState-of-the-art high-performance processors like the IBM POWER5 and Intel i7 show a trend in industry towards on-chip Multiprocessors (CMP) involving Simultaneous Multithreading (SMT) in each core. In these processors, the way in which applications are assigned to cores plays a key role in the performance of each application and the overall system performance. In this paper we show that the system throughput highly depends on the Thread to Core Assignment (TCA), regardless the SMT Instruction Fetch (IFetch) Policy implemented in the cores. Our results indicate that a good TCA can improve the results of any underlying IFetch Policy, yielding speedups of up to 28%. Given the relevance of TCA, we propose an algorithm to manage it in CMP+SMT processors. The proposed throughput-oriented TCA Algorithm takes into account the workload characteristics and the underlying SMT IFetch Policy. Our results show that the TCA Algorithm obtains thread-to-core assignments 3% close to the optimal assignation for each case, yielding system throughput improvements up to 21%.
dc.format.extent8 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.titleThread to core assignment in SMT on-chip multiprocessors
dc.typeArticle
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/SBAC-PAD.2009.13
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://portal.acm.org/citation.cfm?id=1685045
dc.rights.accessOpen Access
local.identifier.drac2197146
dc.description.versionPostprint (published version)
local.citation.authorAcosta, C. A.; Cazorla, F.; Ramirez, A.; Valero, M.
local.citation.publicationNameInternational symposium on computer architecture. Proceedings
local.citation.startingPage67
local.citation.endingPage74


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