Translinear signal processing circuits in standard CMOS FPAA
Document typeConference report
PublisherIEEE Press. Institute of Electrical and Electronics Engineers
Rights accessOpen Access
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In this paper, the implementation of signal processing circuits on a novel translinear Field-Programmable Analog Array (FPAA) testchip is reported. The FPAA testchip is based on a 0.35-micron, fully CMOS translinear element, which is the core block of a reconfigurable analog cell. The FPAA embeds a 5 5 cell array. As implementation examples, a four-quadrant multiplier with five decade dynamic range and a programmable fourth-order low-pass filter with up to 7 MHz bandwidth have been mapped on the translinear FPAA. 14 cells have been used for the four-quadrant multiplier while 18 cells were needed for the fourth-order low-pass filter.
CitationMartínez-Alvarado, L.; Madrenas, J.; Fernandez, D. Translinear signal processing circuits in standard CMOS FPAA. A: 2009 IEEE International Conference on Electronics Circuits and Systems. "2009 IEEE International Conference on Electronics Circuits and Systems". Yasmine Hammamet: IEEE Press. Institute of Electrical and Electronics Engineers, 2009, p. 715-718.