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Translinear signal processing circuits in standard CMOS FPAA

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hdl:2117/6641

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Martínez Alvarado, Luis Arturo
Madrenas Boadas, JordiMés informacióMés informacióMés informació
Fernández Martínez, Daniel
Document typeConference report
Defense date2009-12
PublisherIEEE Press. Institute of Electrical and Electronics Engineers
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
Abstract
In this paper, the implementation of signal processing circuits on a novel translinear Field-Programmable Analog Array (FPAA) testchip is reported. The FPAA testchip is based on a 0.35-micron, fully CMOS translinear element, which is the core block of a reconfigurable analog cell. The FPAA embeds a 5 5 cell array. As implementation examples, a four-quadrant multiplier with five decade dynamic range and a programmable fourth-order low-pass filter with up to 7 MHz bandwidth have been mapped on the translinear FPAA. 14 cells have been used for the four-quadrant multiplier while 18 cells were needed for the fourth-order low-pass filter.
CitationMartínez-Alvarado, L.; Madrenas, J.; Fernandez, D. Translinear signal processing circuits in standard CMOS FPAA. A: 2009 IEEE International Conference on Electronics Circuits and Systems. "2009 IEEE International Conference on Electronics Circuits and Systems". Yasmine Hammamet: IEEE Press. Institute of Electrical and Electronics Engineers, 2009, p. 715-718. 
URIhttp://hdl.handle.net/2117/6641
ISBN978-1-4244-5091-6
Publisher versionhttp://www.icecs2009.org
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