Show simple item record

dc.contributor.authorGupta, Manoj
dc.contributor.authorSánchez Carracedo, Fermín
dc.contributor.authorLlosa Espuny, José Francisco
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-02-25T10:26:28Z
dc.date.available2010-02-25T10:26:28Z
dc.date.created2009-10
dc.date.issued2009-10
dc.identifier.citationGupta, M.; Sánchez, F.; Llosa, J. Hybrid multithreading for VLIW processors. A: International Conference on Compilers, Architecture and Synthesis for Embedded Systems. "2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems". Grenoble: 2009, p. 37-46.
dc.identifier.isbn978-1-60558-629-8
dc.identifier.urihttp://hdl.handle.net/2117/6467
dc.description© ACM, 2009. This is the author's version of the work: http://doi.acm.org/10.1145/1629395.1629403
dc.description.abstractSeveral multithreading techniques have been proposed to reduce resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique that improves processor performance by issuing multiple instructions from di erent threads. In VLIW processors, SMT requires extra hardware to merge instructions from di erent threads. The complexity of this hardware increases substantially with the number of threads. On the other hand, techniques like Interleaved MultiThreading (IMT) do not need any merging hardware, and support a larger number of threads at reasonable cost. In this paper, we propose Hybrid MultiThreading (HMT), a technique that at each cycle merges instructions from only a subset of threads. HMT supports a reasonable number of threads with a low merging hardware cost. For instance, it is possible to support 8 hardware threads with a merging hardware for only 2 threads. The experimental results show that using HMT improves the multithreading performance significantly. Further, supporting 8 hardware threads with HMT but using a 4-thread merging hardware achieves a performance similar to merging 8 threads simultaneously with a significantly lower merging hardware cost.
dc.format.extent10 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshSimultaneous multithreading processors
dc.subject.lcshMicroprocessors
dc.subject.otherClustered VLIW Processors
dc.subject.otherMultithreading
dc.titleHybrid multithreading for VLIW processors
dc.typeConference report
dc.subject.lemacMicroprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
drac.iddocument2358621
dc.description.versionPostprint (author’s final draft)
upcommons.citation.authorGupta, M.; Sánchez, F.; Llosa, J.
upcommons.citation.contributorInternational Conference on Compilers, Architecture and Synthesis for Embedded Systems
upcommons.citation.pubplaceGrenoble
upcommons.citation.publishedtrue
upcommons.citation.publicationName2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
upcommons.citation.startingPage37
upcommons.citation.endingPage46


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

Except where otherwise noted, content on this work is licensed under a Creative Commons license: Attribution-NonCommercial-NoDerivs 3.0 Spain