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Hybrid multithreading for VLIW processors
dc.contributor.author | Gupta, Manoj |
dc.contributor.author | Sánchez Carracedo, Fermín |
dc.contributor.author | Llosa Espuny, José Francisco |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2010-02-25T10:26:28Z |
dc.date.available | 2010-02-25T10:26:28Z |
dc.date.created | 2009-10 |
dc.date.issued | 2009-10 |
dc.identifier.citation | Gupta, M.; Sánchez, F.; Llosa, J. Hybrid multithreading for VLIW processors. A: International Conference on Compilers, Architecture and Synthesis for Embedded Systems. "2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems". Grenoble: 2009, p. 37-46. |
dc.identifier.isbn | 978-1-60558-629-8 |
dc.identifier.uri | http://hdl.handle.net/2117/6467 |
dc.description | © ACM, 2009. This is the author's version of the work: http://doi.acm.org/10.1145/1629395.1629403 |
dc.description.abstract | Several multithreading techniques have been proposed to reduce resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique that improves processor performance by issuing multiple instructions from di erent threads. In VLIW processors, SMT requires extra hardware to merge instructions from di erent threads. The complexity of this hardware increases substantially with the number of threads. On the other hand, techniques like Interleaved MultiThreading (IMT) do not need any merging hardware, and support a larger number of threads at reasonable cost. In this paper, we propose Hybrid MultiThreading (HMT), a technique that at each cycle merges instructions from only a subset of threads. HMT supports a reasonable number of threads with a low merging hardware cost. For instance, it is possible to support 8 hardware threads with a merging hardware for only 2 threads. The experimental results show that using HMT improves the multithreading performance significantly. Further, supporting 8 hardware threads with HMT but using a 4-thread merging hardware achieves a performance similar to merging 8 threads simultaneously with a significantly lower merging hardware cost. |
dc.format.extent | 10 p. |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Simultaneous multithreading processors |
dc.subject.lcsh | Microprocessors |
dc.subject.other | Clustered VLIW Processors |
dc.subject.other | Multithreading |
dc.title | Hybrid multithreading for VLIW processors |
dc.type | Conference report |
dc.subject.lemac | Microprocessadors |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Open Access |
local.identifier.drac | 2358621 |
dc.description.version | Postprint (author’s final draft) |
local.citation.author | Gupta, M.; Sánchez, F.; Llosa, J. |
local.citation.contributor | International Conference on Compilers, Architecture and Synthesis for Embedded Systems |
local.citation.pubplace | Grenoble |
local.citation.publicationName | 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems |
local.citation.startingPage | 37 |
local.citation.endingPage | 46 |