Relative timing verification revisited

dc.contributor.author	Solé Simó, Marc
dc.contributor.author	Pastor Llorens, Enric
dc.contributor.other	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned	2010-01-15T11:59:28Z
dc.date.available	2010-01-15T11:59:28Z
dc.date.issued	2008
dc.identifier.uri	http://hdl.handle.net/2117/6159
dc.description	Technical Report UPC-DAC-RR-CAP-2008-39
dc.description.abstract	Timed verification is a difficult problem. One of the ways in which it can be simplified is by using iterative refinement techniques. Here we investigate the advantages and shortcomings of this approach when combined with relative timing reasoning.
dc.format.extent	328 p.
dc.language.iso	eng
dc.relation.ispartofseries	UPC-DAC-RR-CAP-2008-39
dc.rights	Attribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subject	Àrees temàtiques de la UPC::Informàtica::Programació
dc.subject.lcsh	Formal methods (Computer science)
dc.title	Relative timing verification revisited
dc.type	External research report
dc.subject.lemac	Mètodes formals (Informàtica)
dc.subject.lemac	Programari -- Verificació
dc.contributor.group	Universitat Politècnica de Catalunya. ICARUS - Intelligent Communications and Avionics for Robust Unmanned Aerial Systems
dc.relation.publisherversion	http://gsi.ac.upc.edu/reports/2008/75/frame.ps
dc.rights.access	Open Access
local.identifier.drac	2057622
dc.description.version	Preprint
local.personalitzacitacio	true

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