Now showing items 1-12 of 14

    • Process variability in sub-16nm bulk CMOS technology 

      Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon (2012-03-01)
      External research report
      Open Access
      The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.
    • Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-04-15)
      External research report
      Open Access
      In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations.
    • On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-12-05)
      External research report
      Restricted access - publisher's policy
      In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive ...
    • vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2010-09-05)
      External research report
      Open Access
      In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is ...
    • FOCSI: A new layout regularity metric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
      External research report
      Open Access
      Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ...
    • THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 3: PA+Sensor layout integration and PVT analysis 

      Martín, Mikel; González Jiménez, José Luis (2011-05-16)
      External research report
      Restricted access - publisher's policy
      The objective is to detect the impact of PVT variations (Process, Voltage and Temperature variations) on the figures of merit of a device.
    • THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 2: Temperature Sensor 

      Martín, Mikel; González Jiménez, José Luis (2011-04-25)
      External research report
      Restricted access - publisher's policy
      The temperature sensor used is based on the usual two bipolar transistors temperature sensor with some modifications to allow for external calibration (or “re-centering”).
    • THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 1: Feasibility study 

      Martin, Mikel; González Jiménez, José Luis (2011-03-02)
      External research report
      Restricted access - publisher's policy
      In this Project, the verification of the possibility of extraction of information of a modulated signal through no-invasive thermal measurements is done. The main objective is that using a non-invasive thermal technique, ...
    • CATRENE-PANAMA project review November 2010 

      González Jiménez, José Luis; Dufis, Cédric Yvan (2010-11-23)
      External research report
      Restricted access - confidentiality agreement
      Informe de progrés del projecte Europeu CATRENE-PANAMA sobre les tasques desenvolupades per el grup de recerca HiPICS de la UPC
    • Inforrme de la segona anualitat del projecte CATRENE-PANAMA per al programa AVANZA I+D 

      González Jiménez, José Luis; Dufis, Cédric Yvan (2011-03-16)
      External research report
      Restricted access - confidentiality agreement
      Informe de les tasques i activitats desenvolupades al projecte europeu CATRENE-PANAMA durant l'any 2010 per el grup de recerca de la UPC HiPICS
    • CATRENE-PANAMA project review June 2010 

      González Jiménez, José Luis; Dufis, Cédric Yvan (2010-06-03)
      External research report
      Restricted access - confidentiality agreement
      Informe de progrés del projecte Europeu CATRENE-PANAMA sobre les tasques desenvolupades per el grup de recerca HiPICS de la UPC
    • CATRENE-PANAMA WP1: integrated PA Milestone M1.3 technology, approach & system choice for home networking 

      Dufis, Cédric Yvan; Mateo Peña, Diego; Bofill, Adrià; González Jiménez, José Luis (2009-10-30)
      External research report
      Open Access