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Measurements of process variability in 40-nm regular and nonregular layouts
(2014-02-01)
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As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts ...
Design of complex circuits using the via-configurable transistor array regular layout fabric
(IEEE Computer Society Publications, 2011)
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Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ...
Lithography aware regular cell design based on a predictive technology model
(2010-12)
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As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ...
Lithography aware regular cell design based on a predictive technology model
(2010)
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As semiconductor technology advances into the
nanoscale era, optical effects such as channel narrowing, corner
rounding or line-end pullback are critical to accomplish circuit
yield specifications. It is well-demonstrated ...
Yield estimation model for lithography hotspot distortions
(Institution of Electrical Engineers, 2013-08-15)
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A yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the
yield ...