HIPICS - High Performance Integrated Circuits and Systems
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Altres [1]
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Articles de revista [92]
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Reports de recerca [15]
Recent Submissions
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FastIC: a fast integrated circuit for the readout of high performance detectors
(2022-05-01)
Article
Open AccessThis work presents the 8-channel FastIC ASIC developed in CMOS 65¿nm technology suitable for the readout of positive and negative polarity sensors in high energy physics experiments, Cherenkov detectors and time-of-flight ... -
VCO phase noise and sideband spurs due to substrate noise generated by on-chip digital circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
Conference report
Open AccessThis paper presents the effects of noise generated by realistic digital circuits on RF voltage controlled oscillators (VCO) integrated in the same silicon die. The digital noise is coupled through the common substrate and ... -
Frequency characterization of a 2.4 GHz CMOS LNA by Thermal Measurements
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
Conference report
Open AccessThis paper presents a technique to obtain electrical characteristics of analog and RF circuits, based on measuring temperature at the silicon surface close to the circuit under test. Experimental results validate the ... -
Using temperature as observable of the frequency response of RF CMOS amplifiers
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Conference report
Open AccessThe power dissipated by the devices of an integrated circuit can be considered a signature of the circuit's performance. Without disturbing the circuit operation, this power consumption can be monitored by temperature ... -
A low-power RF front-end for 2.5 GHz receivers
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Conference report
Open AccessThis paper presents a low power and low cost front end for a direct conversion 2.5 GHz ISM band receiver composed of a 16 kV HBM ESD protected LNA, differential Gilbert-cell mixers, and high-pass filters for DC offset ... -
Design and implementation of a 5/spl times/5 trits multiplier in a quasi-adiabatic ternary CMOS logic
(1998-07)
Article
Open AccessAdiabatic switching is a technique to design low-power digital IC's. Fully adiabatic logics have expensive silicon area requirements. To solve this drawback, a quasi-adiabatic ternary logic is proposed. Its basis is ... -
An approach to dynamic power consumption current testing of CMOS ICs
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Conference report
Open AccessI/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can ... -
Implementation of a 5x5 trits multiplier in a quasi-adiabatic ternary CMOS logic
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessAdiabatic switching is one technique to design low power digital IC. In order to diminish its expensive silicon area requirements an adiabatic ternary logic is proposed. A 5×5 trits (ternary signals) multiplier has been ... -
Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Conference report
Open AccessDifference between ISSQ and IDDQ testing strategies is presented, discussing the dependency of area overhead and sensing speed on the technology. The current sensor implementation style suitable for cell-based design ... -
Characterization of the substrate noise spectrum for mixed-signal ICs
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Conference report
Open AccessThis paper presents a simplified analytical model of the substrate noise generated by digital circuitry that captures the most relevant frequency domain characteristics and relates them with parameters of the digital circuit ... -
Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact
(Institute of Electrical and Electronics Engineers (IEEE), 2022-05-02)
Article
Open AccessThis study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 ... -
CMOS inverter performance degradation and its correlation with BTI, HCI and OFF state MOSFETs aging
(2022-05-01)
Article
Restricted access - publisher's policyIn this work, CMOS inverters are subjected to electrical stress emulating a complete operation cycle and the shifts in the performance parameters (i.e., peak current and inversion voltage) evaluated. Moreover, degradation ...
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