Envíos recientes

  • Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level 

    Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Comunicación de congreso
    Acceso restringido por política de la editorial
    This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of ...
  • Experimental time evolution study of the HFO-based IMPLY gate operation 

    Maestro, M; Marin-Martinez, J.; Crespo-Yepes, A.; Escudero, Manel; Rodriguez, R.; Nafria, M.; Aymerich, X.; Rubio Sola, Jose Antonio (2018-02-01)
    Artículo
    Acceso abierto
    In the last years, memristor devices have been proposed as key elements to develop a new paradigm to implement logic gates. In particular, the memristor-based material implication (IMPLY) gate has been presented as a ...
  • Adaptive fault-tolerant architecture for unreliable device technologies 

    Aymerich, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (CRC Press, Taylor and Francis Group, 2013-06-03)
    Capítulo de libro
    Acceso restringido por política de la editorial
    Nanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that ...
  • An on-line test strategy and analysis for a 1T1R crossbar memory 

    Escudero, Manel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Vourkas, Ioannis (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
    Acceso abierto
    Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ...
  • Reliability issues in RRAM ternary memories affected by variability and aging mechanisms 

    Rubio Sola, Jose Antonio; Escudero, Manuel; Pouyan, Peyman (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
    Acceso abierto
    Resistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and ...
  • Análisis del retardo en enlaces con protocolos ARQ y control de flujo: aplicación a una red estrella 

    Rubio Sola, Jose Antonio; Figueras Pàmies, Joan (Marcombo, 1983)
    Texto en actas de congreso
    Acceso abierto
    El objetivo de este trabajo se enmarca en el desarrollo de herramientas de cuantificación de los tiempos de retardo en redes de computadores. El análisis se ha centrado en la evaluación del tiempo medio de retardo en el ...
  • Differential temperature sensor with high sensitivity, wide dynamic range and digital offset calibration 

    Vidal López, Eva María; Ruiz Cayuela, Sergio; Duquenoy, Jérémy; González, J. L.; Altet Sanahujes, Josep (2017-08-15)
    Artículo
    Acceso restringido por política de la editorial
    The goal of this paper is twofold: first to add together all different causes that can alter the offset of a differential temperature sensor and, second, to present a new differential temperature sensor architecture that ...
  • Design of a broadband CMOS RF power amplifier to establish device-circuit aging correlations 

    Barajas Ojeda, Enrique; Mateo Peña, Diego; Aragonès Cervera, Xavier; Crespo Yepes, Albert; Rodríguez Martínez, Rosana; Martin Martínez, Javier; Nafría Maqueda, Montserrat (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    This paper presents the design of a Broadband CMOS RF Power Amplifier, suitable to be stressed at circuit level but with the possibility to be measured both at circuit and at device level. It allows establishing a relation ...
  • Exploring the voltage divider approach for accurate memristor state tuning 

    Vourkas, Ioannis; Gomez, Jorge; Abusleme, Angel; Vasileiadis, Nikolaos; Sirakoulis, Georgios; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    The maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multilevel programming. In this direction, we explore the voltage ...
  • Statistical characterization and modeling of random telegraph noise effects in 65nm SRAM cells 

    Martinez, Javier; Rodriguez, Rosa; Nafria, Montse; Torrents, Gabriel; Bota, Sebastian A .; Segura, Jaume; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    Random Telegraph Noise (RTN) effects are investigated in 65nm SRAM cells by using a new characterization method that provides a significant measurement time reduction. The variability induced in commercial SRAM cells is ...
  • MOSFET degradation dependence on input signal power in a RF power amplifier 

    Crespo Yepes, Albert; Barajas Ojeda, Enrique; Martin Martínez, Javier; Mateo Peña, Diego; Aragonès Cervera, Xavier; Rodríguez Martínez, Rosana; Nafría Maqueda, Montserrat (2017-06-25)
    Artículo
    Acceso abierto
    Aging produced by RF stress is experimentally analyzed on a RF CMOS power amplifier (PA), as a function of the stress power level. The selected circuit topology allows observing individual NMOS and PMOS transistors ...
  • Via-configurable transistors array: a regular design technique to improve ICs yield 

    Pons, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Texto en actas de congreso
    Acceso abierto
    Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ...

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