Hypervisor extension for a RISC-V processor
Cita com:
hdl:2117/414131
Document typeConference lecture
Defense date2023
Rights accessOpen Access
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ProjectVitamin-V - Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services (EC-HE-101093062)
UPC-COMPUTACION DE ALTAS PRESTACIONES VIII (AEI-PID2019-107255GB-C22)
UPC-COMPUTACION DE ALTAS PRESTACIONES VIII (AEI-PID2019-107255GB-C22)
Abstract
This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one.
CitationGauchola, J. [et al.]. Hypervisor extension for a RISC-V processor. A: RISC-V Summit Europe. "ISC-V Summit Europe 2023: Experience the future of open computing in Europe". 2023.
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- Doctorat en Arquitectura de Computadors - Ponències/Comunicacions de congressos [311]
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.976]
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