Ethernet emulation over PCIe for RISC-V software development vehicles
Cita com:
hdl:2117/408106
Document typeConference report
Defense date2023
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
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Abstract
This paper describes two different approaches to emulate an Ethernet communication link between a host computer and a RISC-V multiprocessor system running on a FPGA accelerator by using PCIe as the real communication link. Two approaches are tested, one based on user-level applications using TUN/TAP drivers and another based on implemented kernel-mode drivers on the Linux Operation System. We have functionally validated the approaches in multiple RISC-V systems and measured the achieved performance. A maximum bandwidth of 32.5 Mbps has been achieved in a Lagarto Hun system running at 100 Mhz.
CitationCastells, D. [et al.]. Ethernet emulation over PCIe for RISC-V software development vehicles. A: Conference on Design of Circuits and Integrated Systems. "38th Conference on Design of Circuits and Integrated Systems (DCIS 2023): Pamplona, Spain: November 15-17, 2023: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2023. ISBN 979-8-3503-0385-8. DOI 10.1109/DCIS58620.2023.10335994.
ISBN979-8-3503-0385-8
Publisher versionhttps://ieeexplore.ieee.org/document/10335994
Collections
- Doctorat en Arquitectura de Computadors - Ponències/Comunicacions de congressos [314]
- Computer Sciences - Ponències/Comunicacions de congressos [601]
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.979]
- PM - Programming Models - Ponències/Comunicacions de congressos [16]
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