In Hard Real-time Systems, the execution of tasks must be completed within a certain timeframe, known as deadline. In consequence, when a hard-real time system is designed, it is strictly necessary to assume that its tasks will always take their Worst Case Execution Time (WCET), to make sure they meet their deadlines. For this reason, Worst Case Execution Times defines the maximum performance of processors in these systems. Since the performance requirements of modern Hard Real-time Systems are rapidly increasing, the use of newer and higher performance processors is needed. However, these processors have a much greater internal complexity compared to the ones previously used in these systems. This complexity can be detrimental given that Worst Case Execution Times, which are critical for these systems, are often estimated using traditional timing analysis methods like Static and Measurement-based deterministic techniques. The need for extremely detailed knowledge of the processor's internals, IP restrictions, and the impossibility of modeling certain features leads to extremely pessimistic assumptions and the disabling of features while using these techniques. On the other hand, Measurement-Based Probabilistic Timing Analysis (MBPTA) allows computing probabilistic WCET estimates easily on top of more complex hardware. This can only be performed when Time Randomisation is introduced in the microarchitectural design, e.g. namely through time-randomised cache designs. Despite their better WCET compared to conventional caches, time-randomised caches provide lower average performance. In this work, we perform the following contributions. First, we add MBPTA support in a commercial RISC-V processor for real-time systems. We show how branch prediction can become MBPTA-compliant, and in conjunction with a cache-locking mechanism can increase the front-end performance of an MBPTA compliant processor. Our evaluation demonstrates benefits both in terms of average case as well as in worst case performance.
