A Low-Power High-Resolution Delta-Sigma ADC IP in 22 nm CMOS Technology for Smart Sensing Applications

Abstract

The present project comprises the third generation of $\Delta\Sigma$ ADCs developed at the IMB-CNM with the design of a 16-bit 50-kHz $\Delta\Sigma$ modulator circuit as a mixed-signal IP block in the 22-nm 0.8-V FD-SOI CMOS technology from Global Foundries. A top-down methodology of mixed-signal ICs has been followed to design the IP, aiming to achieve a Schreier FoM of at least 180 dB. The complexity of the design and the time limitation has made it impossible to reach the layout stage since the PSD of the schematic phase has shown distortion that must be further investigated. Nevertheless, the noise shaper works as expected and a reduced analog power consumption has been obtained. After all, the new topologies implemented in the operational amplifiers and the SAR quantizer algorithms offer a new perspective for further designs within the ICAS research group.