Design of a 12-bit ramp ADC in 250 nm for image sensor ICs

Abstract

This thesis presents the design of a 12-bit single slope ADC embedded in an image sensor integrated circuit (IC) that takes advantage of the signal-dependent photon-shot noise characteristic inherent in image sensors. It is implemented using a column ADC architecture and incorporates a digital double sampling technique for removing the possible non-linearities. The circuit has been thoroughly studied and designed from a theoretical standpoint, and the performance and robustness of each sub-block have been ensured under various PVT and Montecarlo simulations. Finally, the layout of the analog domain of the ADC column has been completed in a 250nm CMOS process