OpenPiton optimizations towards high performance manycores

Abstract

In recent years, numerous multicore RISC-V platforms have emerged. Within the RISC-V ecosystem, Networks-on-Chip (NoCs) such as OpenPiton are employed in designs that aim to scale to a large number of cores. This paper presents a set of extensions and optimizations to OpenPiton for high-performance manycores. The key contributions are enabling multiple memory controllers, supporting router bypassing and NoC concentration, and adding support for configurable cache sizes and cache block sizes. On a 64-core manycore architecture, these new features and optimizations provide a geometric mean speedup of 6.5x compared to the OpenPiton baseline.