dc.contributor.author | Rallis, Konstantinos |
dc.contributor.author | Fyrigos, Iosif-Angelos |
dc.contributor.author | Dimitrakis, Panagiotis |
dc.contributor.author | Dimitrakopoulos, George N. |
dc.contributor.author | Karafyllidis, Ioannis |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.author | Sirakoulis, Georgios Ch. |
dc.contributor.other | Universitat Politècnica de Catalunya. Doctorat en Enginyeria Electrònica |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2024-01-16T07:29:13Z |
dc.date.available | 2024-01-16T07:29:13Z |
dc.date.issued | 2023 |
dc.identifier.citation | Rallis, K. [et al.]. A reprogrammable graphene nanoribbon-based logic gate. "IEEE transactions on nanotechnology", 2023, vol. 22, p. 684-695. |
dc.identifier.issn | 1536-125X |
dc.identifier.uri | http://hdl.handle.net/2117/399556 |
dc.description | © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
dc.description.abstract | In this article, taking into consideration the exceptional technological properties of a unique 2-D material, namely Graphene, we are envisioning its usage as the structure material of a non-back-gated re-programmable switching device. The proposed topology is analyzed in depth, not only by verifying its operation and re-programmability as a 2-input XOR , 3-input XOR and 3-input Majority gate, but also by examining its computing performance in terms of area, delay and power dissipation. More specifically, we are utilizing L-shaped Graphene Nanoribbons (GNRs) to develop comb-shaped Graphene based switching devices. These devices are in position with effective programming through biasing to design any combinatorial circuit as resulting from the aforementioned universal set of Boolean gates. The resulting figures of merit regarding the area with a universal footprint of 2.53 nm2 for every gate independently of the number of inputs, the propagation delay with 2.05×10-2ps and, last but not least, the power dissipation with only 10.204 nW for the gates with greater number of inputs, are quite encouraging and promising. Moreover, the ability of the proposed topology to pave the way towards the implementation of basic circuits has been further investigated, by demonstrating an example of a 1-bit full adder cell and its sufficient operation arriving from the corresponding successful SPICE simulation results. |
dc.format.extent | 12 p. |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 International |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Integrated circuits |
dc.subject.lcsh | Graphene |
dc.subject.other | Graphene |
dc.subject.other | Logic gates |
dc.subject.other | Switches |
dc.subject.other | Photonic band gap |
dc.subject.other | Nanoribbons |
dc.subject.other | Fabrication |
dc.title | A reprogrammable graphene nanoribbon-based logic gate |
dc.type | Article |
dc.subject.lemac | Circuits integrats |
dc.subject.lemac | Grafè |
dc.contributor.group | Universitat Politècnica de Catalunya. EFRICS - Efficient and Robust Integrated Circuits and Systems |
dc.identifier.doi | 10.1109/TNANO.2023.3323397 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/10275008?source=authoralert |
dc.rights.access | Open Access |
local.identifier.drac | 37295440 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-103869RB-C33/ES/THE VARIABILITY CHALLENGE IN NANO-CMOS AND BEYOND-CMOS: NOVEL IC DESIGN PARADIGMS FOR MITIGATION AND EXPLOITATION (VIGILANT-UPC)/ |
local.citation.author | Rallis, K.; Fyrigos, I.; Dimitrakis, P.; Dimitrakopoulos, G.; Karafyllidis, I.; Rubio, A.; Sirakoulis, Georgios |
local.citation.publicationName | IEEE transactions on nanotechnology |
local.citation.volume | 22 |
local.citation.startingPage | 684 |
local.citation.endingPage | 695 |