Departament d'Arquitectura de Computadors: Enviaments recents
Ara es mostren els items 13-24 de 3275
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Energy hardware and workload aware job scheduling towards interconnected HPC environments
(2021-06-17)
Article
Accés obertNew HPC machines are getting close to the exascale. Power consumption for those machines has been increasing, and researchers are studying ways to reduce it. A second trend is HPC machines' growing complexity, with increasing ... -
Charging of the ABR service in ATM networks: a numerical example
(Institute of Electrical and Electronics Engineers (IEEE), 1998-04)
Article
Accés obertThe Available Bit Rate service (ABR) is a "best effort" service intended for traffic which imposes no bound on delay or delay variation. The network guarantees a Minimum Cell Rate (MCR) for an ABR source, which is negotiated ... -
δLTA:: Decoupling camera sampling from processing to avoid redundant computations in the vision pipeline
(Association for Computing Machinery (ACM), 2023)
Text en actes de congrés
Accés obertContinuous Vision (CV) systems are essential for emerging applications like Autonomous Driving (AD) and Augmented/Virtual Reality (AR/VR). A standard CV System-on-a-Chip (SoC) pipeline includes a frontend for image capture ... -
SLIDEX: Sliding window extension for image processing
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertWith the rising need for efficient image processing in emerging applications such as Autonomous Driving (AD) and Augmented/Virtual Reality (AR/VR), many existing solutions do not meet their performance and energy efficiency ... -
QeiHaN: An energy-efficient DNN accelerator that leverages log quantization in NDP architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertThe constant growth of DNNs makes them challenging to implement and run efficiently on traditional computecentric architectures. Some works have attempted to enhance accelerators by adding more compute units and on-chip ... -
Improving the discovery and clustering of three-dimensional protein patterns with OpenMP
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertThe discovery of conserved three-dimensional (3D) amino-acid patterns among a set of protein structures can be useful, for instance, to predict the functions of unknown proteins or for the rational design of multi-target ... -
O(n) key–value sort with active compute memory
(Institute of Electrical and Electronics Engineers (IEEE), 2024-02-29)
Article
Accés obertWe propose the Active Compute Memory (ACM), a near-memory-processing architecture capable of performing key–value sort directly in the DRAM. In the ACM architecture, sort is merely the writing of data into memory with one ... -
Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials
(SAGE publishing, 2023-07)
Article
Accés obertThe Abisko project aims to develop an energy-efficient spiking neural network (SNN) computing architecture and software system capable of autonomous learning and operation. The SNN architecture explores novel neuromorphic ... -
Finding, analysing and solving MPI communication bottlenecks in Earth System models
(Elsevier, 2019-09)
Article
Accés obertIt is a matter of consensus that the ability to efficiently use current and future high performance computing systems is crucial for science, however, the reality is that the performance currently achieved by most of the ... -
Boustrophedonic frames: Quasi-optimal L2 caching for textures in GPUs
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertLiterature is plentiful in works exploiting cache locality for GPUs. A majority of them explore replacement or bypassing policies. In this paper, however, we surpass this exploration by fabricating a formal proof for a ... -
MNEMOSENE++: Scalable multi-tile design with enhanced buffering and VGSOT-MRAM based compute-in-memory crossbar array
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertThis paper optimizes the MNEMOSENE architecture, a compute-in-memory (CiM) tile design integrating computation and storage for increased efficiency. We identify and address bottlenecks in the Row Data (RD) buffer that cause ... -
Performance-oriented digital twins for packet and optical networks
(2023-10-23)
Report de recerca
Accés obertThis draft introduces the concept of a Network Digital Twin (NDT), including the architecture as well as the interfaces. Then two specific instances of the NDT are introduced, the first one for packet networks. This ...