Physical design of a RISC-V processor with accelerators chip in 22nm FDSOI technology
Document typeMaster thesis
Rights accessOpen Access
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This thesis contains the physical design for the Kameleon chip as well as for its processing cores IP. The Kameleon chip is a digital SoC containing 2 cores as well as multiple accelerators developed by the DRAC partnership. Firstly, we explain our goals for the working frequencies of the finished design, as well as a description of the different IPs to be integrated within it and their functions. Then a step by step explanation of the physical designs for the Cores IP and Kameleon SoC is presented. Lastly an analysis is made of the physical designs, where we find out that we have managed to make a working design even if the frequencies that can be achieved are a bit lower than what we had hoped for.