Experimental analysis on the NXP’s T2080 cache coherence: a step towards MPSoCs in critical systems

Abstract

The adoption of complex MPSoCs in critical real-time embedded systems [1], [2] mandates a detailed analysis of their architecture to facilitate certification [3]. This analysis is hindered by the lack of a thorough understanding of the MPSoC system due to the unobvious and/or insufficiently documented behavior of some key hardware features [4], [5]. Confidence in those features can only be regained by building specific tests to both, assess whether their behavior matches specifications and unveil their behavior when it is not fully known a priori. In this line, in this work we develop a thorough understanding of the cache coherence protocol in the avionics-relevant [6] NXP T2080 [1] architecture.