b8c: an FPGA-friendly sparse matrix representation suitable for the SpMV kernel

Abstract

Sparse Matrix-Vector multiplication (SpMV), computing y = Ax where y and x are dense vectors and A is a sparse matrix, is a key kernel in many HPC applications. SpMV exhibits a kind of memory access that is extremely hard to perform efficiently, due to its random access. In the case of FPGAs, which lack a “default” memory hierarchy including caches to hide the latency of main memory, obtaining good performance when running SpMV is specially challenging. In our work, we have explored different approaches to the SpMV implementation on FPGAs, which have result in the definition of a new sparse matrix encoding format (b8c) and its corresponding SpMV implementation using OmpSs@FPGA. In our tests, the b8c SpMV implementation shows x25 performance improvement when compared to an HLS-optimized Compressed Sparse-Row (CSR) FPGA version and offers, running at 100MHz, 20% of the performance of a single-core Ryzen 7 running at 3.9GHz and using the same CSR format.