DVINO: A RISC-V vector processor implemented in 65nm technology

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hdl:2117/382730
Document typeConference lecture
Defense date2022
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
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Abstract
This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.
CitationCabo, G. [et al.]. DVINO: A RISC-V vector processor implemented in 65nm technology. A: Conference on Design of Circuits and Integrated Systems. "DCIS 2022: proceedings of the 37th Conference on Design of Circuits and Integrated Systems: Pamplona, Navarra, 16-18 November 2022". Institute of Electrical and Electronics Engineers (IEEE), 2022, ISBN 978-1-6654-5950-1. DOI 10.1109/DCIS55711.2022.9970128.
ISBN978-1-6654-5950-1
Publisher versionhttps://ieeexplore.ieee.org/document/9970128
Collections
- Doctorat en Arquitectura de Computadors - Ponències/Comunicacions de congressos [251]
- Computer Sciences - Ponències/Comunicacions de congressos [530]
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.874]
- Departament d'Enginyeria Electrònica - Ponències/Comunicacions de congressos [1.665]
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