Functional verification of a RISC-V vector accelerator
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
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We present the functional verification efforts for an academic RISC-V based vector accelerator, successfully taped-out in the context of the European Processor Initiative. For our novel RISC-V based decoupled vector accelerator, we built a verification infrastructure consisting of a UVM environment, performing step by step co-simulation of all vector instructions, using the Spike instruction set simulator as a reference model. Furthermore, for validating this complex design connected to a scalar core using a custom interface, we provided automated constrained-random test generation, simulation and error reporting, and CI/CD infrastructure. We found 3005 errors during this process and reached 95.79% functional coverage.
CitationJiménez, V. [et al.]. Functional verification of a RISC-V vector accelerator. "IEEE design & test", Juny 2023, vol. 40, núm. 3, p. 36-44.