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dc.contributorMateo Peña, Diego
dc.contributorBofill Petit, Adria
dc.contributor.authorGómez Navarro, Marc
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2023-02-08T12:47:36Z
dc.date.issued2022-05-27
dc.identifier.urihttp://hdl.handle.net/2117/382674
dc.description.abstractThis thesis presents a sub low voltage differential signalling (sub-LVDS) transmitter for a high-speed serial interface application in an image sensor integrated circuit (IC). The targeted data rate of the circuit is 0.89 Gbps while using 180 nm CMOS technology and a 1.8V power supply. The sub-LVDS works with a common mode voltage of 800 mV and provides an output swing of 400 mV in the receiver side. In this work, the circuit has been studied and designed from a theoretical point of view and the well-performance and robustness of each of the sub-blocks of the circuit is shown under PVT and Montecarlo simulations. Additionally, the layout of the circuit has also been developed, resulting in a total area of 0.034 mm2.
dc.language.isoeng
dc.publisherUniversitat Politècnica de Catalunya
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica
dc.subject.lcshMicroelectronics--Design
dc.subject.otherElectronics
dc.subject.otherMicroelectronic design
dc.subject.otheranalog design
dc.subject.othersub-LVDS
dc.titleDevelopment of high-speed serial interface output link for image sensor ICs
dc.typeMaster thesis
dc.subject.lemacMicroelectrònica--Disseny
dc.identifier.slugETSETB-230.165832
dc.rights.accessRestricted access - confidentiality agreement
dc.date.lift2028-02-08T12:47:37Z
dc.date.updated2022-10-26T05:50:45Z
dc.audience.educationlevelMàster
dc.audience.mediatorEscola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona
dc.contributor.covenanteeImasenic Advanced Imaging


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