Development of high-speed serial interface output link for image sensor ICs

Abstract

This thesis presents a sub low voltage differential signalling (sub-LVDS) transmitter for a high-speed serial interface application in an image sensor integrated circuit (IC). The targeted data rate of the circuit is 0.89 Gbps while using 180 nm CMOS technology and a 1.8V power supply. The sub-LVDS works with a common mode voltage of 800 mV and provides an output swing of 400 mV in the receiver side. In this work, the circuit has been studied and designed from a theoretical point of view and the well-performance and robustness of each of the sub-blocks of the circuit is shown under PVT and Montecarlo simulations. Additionally, the layout of the circuit has also been developed, resulting in a total area of 0.034 mm2.