Two examples of approximate arithmetic to reduce hardware complexity and power consumption
Cita com:
hdl:2117/381481
Document typeConference lecture
Defense date2022
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
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Abstract
As the end of Moore's Law approaches, electronic system designers must find ways to keep up with the ever increasing computational demands of the modern era. Some computationally intensive applications, such as multimedia processing, computer vision and artificial intelligence, present a unique feature that makes them especially suitable for hardware-level optimizations: their inherent robustness to noise and errors. This allows circuit designers to relax the constraint that arithmetic operations, such as multiplications and additions, must be completely accurate. Instead, approximations can be used in the arithmetic units, enabling system-level reductions in hardware area and power consumption, as well as improvements in performance, while hardly affecting the output of the final application. In this work, we explore two approximate arithmetic techniques. First, we consider approximations at the circuit design level by implementing several approximate multiplier units and evaluating their accuracy when used in executing YOLOv3, a state-of-the-art camera-based object detection deep neural network. Second, we apply the technique of overscaling to induce approximations in adder circuits by aggressively undervoltaging and overclocking them, and we compare the behavior of exact and approximate adders under these conditions. We find that, on one hand, some approximate multipliers are able to execute the YOLO network with almost no effect on the results, and on the other, approximate adder circuits are much more resilient to overscaling techniques than exact adders.
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CitationFornt, J. [et al.]. Two examples of approximate arithmetic to reduce hardware complexity and power consumption. A: Conference on Design of Circuits and Integrated Systems. "37th Conference on Design of Circuits and Integrated Systems (DCIS 2022): Pamplona, Spain: november 16-18, 2022: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2022, p. 1-6. ISBN 978-1-6654-5950-1. DOI 10.1109/DCIS55711.2022.9970160.
ISBN978-1-6654-5950-1
Publisher versionhttps://ieeexplore.ieee.org/document/9970160
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