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SynFull-RTL: evaluation methodology for RTL NoC designs
dc.contributor.author | Leyva Santes, Neiel Israel |
dc.contributor.author | Monemi, Alireza |
dc.contributor.author | Vallejo Gutiérrez, Enrique |
dc.contributor.other | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors |
dc.date.accessioned | 2022-10-04T09:45:04Z |
dc.date.available | 2022-10-04T09:45:04Z |
dc.date.issued | 2022-12 |
dc.identifier.citation | Leyva, N.; Monemi, A.; Vallejo-Gutiérrez, E. SynFull-RTL: evaluation methodology for RTL NoC designs. "IEEE design & test", Desembre 2022, vol. 39, núm, 6, p. 58-69. |
dc.identifier.issn | 2168-2356 |
dc.identifier.uri | http://hdl.handle.net/2117/373906 |
dc.description.abstract | SynFull is a widely employed tool that generates realistic traffic patterns for the performance evaluation of a NoC. In this work, we identify the main limitations of SynFull: high variability and long simulation time and also that these limitations increase when SynFull is integrated with RTL designs. SynFull-RTL employs a statistical approach, simulating each application macro-phase only once and averaging according to its probability of occurrence and the measured traffic load. SynFull-RTL obtains higher accuracy than the original version and reduced variability, with observed 40× reduction in simulation time and resources. A use-case with ProSMART validates the results. |
dc.description.sponsorship | This work has been supported by the Spanish Science and Technology Commission under contract PID2019-105660RB-C22 and the European HiPEAC Network of Excellence. Enrique Vallejo has been partially supported by the Ministry of Universities, Subprograma Estatal de Movilidad, grant number PRX21/00757. This work also received funding from the European Union Horizon 2020 research and innovation programme under grant agreements number 826647 (EPI) and 946002 (MEEP). |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors |
dc.subject.lcsh | Telecommunication -- Traffic -- Management |
dc.subject.other | SynFull |
dc.subject.other | Verilator |
dc.title | SynFull-RTL: evaluation methodology for RTL NoC designs |
dc.type | Article |
dc.subject.lemac | Telecomunicació -- Tràfic -- Gestió |
dc.identifier.doi | 10.1109/MDAT.2022.3202996 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/9870742 |
dc.rights.access | Open Access |
local.identifier.drac | 34251892 |
dc.description.version | Postprint (author's final draft) |
local.citation.author | Leyva, N.; Monemi, A.; Vallejo-Gutiérrez, E. |
local.citation.publicationName | IEEE design & test |
local.citation.volume | 39 |
local.citation.number | 6 |
local.citation.startingPage | 58 |
local.citation.endingPage | 69 |
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