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Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design
dc.contributor.author | Rullán Ayza, Mercedes |
dc.contributor.author | Ferrer Ramis, Carles |
dc.contributor.author | Oliver, Joan |
dc.contributor.author | Mateo Peña, Diego |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2022-09-15T10:41:45Z |
dc.date.available | 2022-09-15T10:41:45Z |
dc.date.issued | 1996 |
dc.identifier.citation | Rullán, M. [et al.]. Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design. A: European Design and Test Conference. "European Design & Test Conference: ED&TC 96: Paris, France: March 11-14, 1996: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1996, p. 584-588. ISBN 0-8186-7424-5. DOI 10.1109/EDTC.1996.494360. |
dc.identifier.isbn | 0-8186-7424-5 |
dc.identifier.uri | http://hdl.handle.net/2117/372844 |
dc.description | © 1996 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
dc.description.abstract | Difference between ISSQ and IDDQ testing strategies is presented, discussing the dependency of area overhead and sensing speed on the technology. The current sensor implementation style suitable for cell-based design methodology or semi-custom design style is proposed Experimental results for each strategy are discussed. Finally, different types of partitioning strategies are showed, taken into account the parallelism of the gates. |
dc.format.extent | 5 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Integrated circuits |
dc.subject.other | Circuit testing |
dc.subject.other | CMOS technology |
dc.subject.other | Rails |
dc.subject.other | Variable structure systems |
dc.subject.other | Design methodology |
dc.subject.other | Logic testing |
dc.subject.other | Monitoring |
dc.subject.other | Libraries |
dc.subject.other | Circuit faults |
dc.subject.other | Integrated circuit interconnections |
dc.title | Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design |
dc.type | Conference report |
dc.subject.lemac | Circuits integrats |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/EDTC.1996.494360 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/494360 |
dc.rights.access | Open Access |
local.identifier.drac | 2327591 |
dc.description.version | Postprint (published version) |
local.citation.author | Rullán, M.; Ferrer, C.; Oliver, J.; Mateo, D.; Rubio, A. |
local.citation.contributor | European Design and Test Conference |
local.citation.publicationName | European Design & Test Conference: ED&TC 96: Paris, France: March 11-14, 1996: proceedings |
local.citation.startingPage | 584 |
local.citation.endingPage | 588 |