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dc.contributor.authorRullán Ayza, Mercedes
dc.contributor.authorFerrer Ramis, Carles
dc.contributor.authorOliver, Joan
dc.contributor.authorMateo Peña, Diego
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2022-09-15T10:41:45Z
dc.date.available2022-09-15T10:41:45Z
dc.date.issued1996
dc.identifier.citationRullán, M. [et al.]. Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design. A: European Design and Test Conference. "European Design & Test Conference: ED&TC 96: Paris, France: March 11-14, 1996: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1996, p. 584-588. ISBN 0-8186-7424-5. DOI 10.1109/EDTC.1996.494360.
dc.identifier.isbn0-8186-7424-5
dc.identifier.urihttp://hdl.handle.net/2117/372844
dc.description© 1996 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractDifference between ISSQ and IDDQ testing strategies is presented, discussing the dependency of area overhead and sensing speed on the technology. The current sensor implementation style suitable for cell-based design methodology or semi-custom design style is proposed Experimental results for each strategy are discussed. Finally, different types of partitioning strategies are showed, taken into account the parallelism of the gates.
dc.format.extent5 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshIntegrated circuits
dc.subject.otherCircuit testing
dc.subject.otherCMOS technology
dc.subject.otherRails
dc.subject.otherVariable structure systems
dc.subject.otherDesign methodology
dc.subject.otherLogic testing
dc.subject.otherMonitoring
dc.subject.otherLibraries
dc.subject.otherCircuit faults
dc.subject.otherIntegrated circuit interconnections
dc.titleAnalysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design
dc.typeConference report
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/EDTC.1996.494360
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/494360
dc.rights.accessOpen Access
local.identifier.drac2327591
dc.description.versionPostprint (published version)
local.citation.authorRullán, M.; Ferrer, C.; Oliver, J.; Mateo, D.; Rubio, A.
local.citation.contributorEuropean Design and Test Conference
local.citation.publicationNameEuropean Design & Test Conference: ED&TC 96: Paris, France: March 11-14, 1996: proceedings
local.citation.startingPage584
local.citation.endingPage588


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