Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
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Difference between ISSQ and IDDQ testing strategies is presented, discussing the dependency of area overhead and sensing speed on the technology. The current sensor implementation style suitable for cell-based design methodology or semi-custom design style is proposed Experimental results for each strategy are discussed. Finally, different types of partitioning strategies are showed, taken into account the parallelism of the gates.
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CitationRullán, M. [et al.]. Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design. A: European Design and Test Conference. "European Design & Test Conference: ED&TC 96: Paris, France: March 11-14, 1996: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1996, p. 584-588. ISBN 0-8186-7424-5. DOI 10.1109/EDTC.1996.494360.