SP4 - Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization
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hdl:2117/372165
Tipus de documentText en actes de congrés
Data publicació2022-05
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Reconeixement-NoComercial-SenseObraDerivada 4.0 Internacional
Abstract
Recent breakthroughs in machine learning (ML)
technology are shifting the boundaries of what is technologically
possible in several areas of Computer Science and Engineering.
This paper discusses ML in the context of test-related activities,
including fault diagnosis, post-silicon validation and yield optimization.
ML is by now an established scientific discipline, and a large
number of successful ML techniques have been developed over
the years. This paper focuses on how to adapt ML approaches
that were originally developed with other applications in mind
to test-related problems. We consider two specific applications of
learning in more depth: delay fault diagnosis in three-dimensional
integrated circuits and tuning performed during post-silicon
validation. Moreover, we examine the emerging concept of braininspired
hyperdimensional computing (HDC) and its potential for
addressing test and reliability questions. Finally, we show how
to integrate ML into actual industrial test and yield-optimization
flows.
CitacióAmrouch, H. [et al.]. SP4 - Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization. A: 27th IEEE European Test Symposium (ETS). 2022,
Versió de l'editorhttps://ieeexplore.ieee.org/xpl/conhome/9810327/proceeding
Fitxers | Descripció | Mida | Format | Visualitza |
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SP4-1.pdf | 1,495Mb | Accés restringit |