dc.contributor.author | Fieback, Moritz |
dc.contributor.author | Münch, Christopher |
dc.contributor.author | Gebregiorgis, Anteneh |
dc.contributor.author | Cardoso Medeiros, Guilherme |
dc.contributor.author | Taouil, Mottaqiallah |
dc.contributor.author | Hamdioui, Said |
dc.contributor.author | Tahoori, Mehdi |
dc.date.accessioned | 2022-07-08T08:41:00Z |
dc.date.issued | 2022-05 |
dc.identifier.citation | Fieback, M. [et al.]. S8 - PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory. A: 27th IEEE European Test Symposium (ETS). 2022, |
dc.identifier.uri | http://hdl.handle.net/2117/372160 |
dc.description.abstract | Emerging non-volatile resistive memories like Spin-
Transfer Torque Magnetic Random Access Memory (STTMRAM)
and Resistive RAM (RRAM) are in the focus of
today’s research. They offer promising alternative computing
architectures such as computation-in-memory (CiM) to reduce
the transfer overhead between CPU and memory, usually referred
to as the memory wall, which is present in all von
Neumann architectures. A multitude of architectures with CiM
capabilities are based on these devices, due to their inherent
resistive behavior and thus their ability to perform calculation
directly within the memory, and thus without invoking the CPU at
all. However, emerging memories are sensitive to Process, Voltage
and Temperature (PVT) variations. This sensitivity has an even
larger impact on CiM architectures. In this paper, we analyze
and compare the impact of PVT variations on STT-MRAM
and RRAM-based CiM architectures. We perform a sensitivity
analysis to identify which parts of the CiM structure are most
susceptible to PVT variations, for each technology. Based on
these analyses, we recommend that STT-MRAM is used in highperformance
CiM, while RRAM is used for edge CiM. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 International |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica |
dc.subject.lcsh | Microelectronics |
dc.subject.lcsh | Integrated circuits |
dc.subject.lcsh | Spintronics |
dc.subject.other | Computation-in-Memory (CiM) |
dc.subject.other | PVT |
dc.subject.other | Emerging memories |
dc.subject.other | STT-MRAM |
dc.subject.other | RRAM |
dc.subject.other | Reliability |
dc.title | S8 - PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory |
dc.type | Conference report |
dc.subject.lemac | Microelectrònica |
dc.subject.lemac | Circuits integrats |
dc.subject.lemac | Espintrònica |
dc.relation.publisherversion | https://ieeexplore.ieee.org/xpl/conhome/9810327/proceeding |
dc.rights.access | Restricted access - publisher's policy |
dc.date.lift | 10000-01-01 |
local.citation.contributor | 27th IEEE European Test Symposium (ETS) |