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dc.contributor.authorAngione, F.
dc.contributor.authorBernardi, P.
dc.contributor.authorFilipponi, G.
dc.contributor.authorSonza Reorda, M.
dc.contributor.authorAppello, D.
dc.contributor.authorTancorre, V.
dc.contributor.authorUgioli, R.
dc.date.accessioned2022-07-08T08:39:00Z
dc.date.available2022-09-01T09:41:47Z
dc.date.issued2022-05
dc.identifier.citationAngione, F. [et al.]. S7 - An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip. A: 27th IEEE European Test Symposium (ETS). 2022,
dc.identifier.urihttp://hdl.handle.net/2117/372158
dc.description.abstractThe complexity of automotive Systems-on-a-Chip (SoCs) has enormously grown in the last decades. Today’s automotive SoCs are compelling due to technology improvements, different integration technologies, increased heterogeneity, and many available embedded memories. On balance, despite testing techniques that have been refined through years, traditional structural test methods, like scan and BIST, can cover a vast but not complete spectrum of all the possible defects. It appears that the divide-and-conquer approach founded on structural techniques may not be enough to reach every single element or to effectively stimulate the faulty behaviors that may show up during the lifetime of the device. Burn-In is widely used to reduce Infant Mortality, accelerating the evolution of weak points into defects via externally or internally induced stress. In this work, we focus on internal stress and present a generation strategy intended to automatically produce functional stress procedures for the Burn-In phase that exacerbate possible weak points which are likely to escape activation by structural tests, such that they more easily outbreak during the successive final test procedures. The proposed generation strategy primarily addresses the interconnections to embedded memories, which look challenging to stress by structural methods, including Logic and Memory BIST, and critical due to the integration of different technologies (i.e., logic gates and memory layout). In the considered test case, the proposed approach increases the average toggle activity by orders of magnitude with respect to Memory BIST. Furthermore, it provides a uniform distributed toggling activity. Results collected on an automotive SoC show how the stress provided by functional programs compares with the stress level provided by structural test methods measured in terms of toggling activity. The SpeedUp produced by the proposed procedure is 3.14X wrt to the MBIST executing the March C-algorithm.
dc.format.extent6 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 International
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica
dc.subject.lcshMicroelectronics
dc.subject.lcshIntegrated circuits
dc.subject.lcshSpintronics
dc.subject.otherDependability
dc.subject.otherBurn-In
dc.subject.otherSystem Level Test
dc.subject.otherSoC
dc.subject.otherInterconnection logic to embedded memories
dc.titleS7 - An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip
dc.typeConference report
dc.subject.lemacMicroelectrònica
dc.subject.lemacCircuits integrats
dc.subject.lemacEspintrònica
dc.relation.publisherversionhttps://ieeexplore.ieee.org/xpl/conhome/9810327/proceeding
dc.rights.accessRestricted access - publisher's policy
local.citation.contributor27th IEEE European Test Symposium (ETS)


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