S5 - Enabling Coverage-Based Verification in Chisel
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hdl:2117/372150
Tipus de documentText en actes de congrés
Data publicació2022-05
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Reconeixement-NoComercial-SenseObraDerivada 4.0 Internacional
Abstract
Ever-increasing performance demands are pushing
hardware designers towards designing domain-specific accelerators.
This has created a demand for improving the overall
efficiency of the hardware design and verification cycles. The
design efficiency was improved with the introduction of Chisel.
However, verification efficiency has yet to be tackled. One method
that can increase verification efficiency is the use of various
types of coverage measures. In this paper, we present our opensource,
coverage-related verification tools targeting digital designs
described in Chisel. Specifically, we have created a new method
allowing for statement coverage at an intermediate representation
of Chisel, and several methods for gathering functional coverage
directly on a Chisel description.
CitacióDobis, A. [et al.]. S5 - Enabling Coverage-Based Verification in Chisel. A: 27th IEEE European Test Symposium (ETS). 2022,
Versió de l'editorhttps://ieeexplore.ieee.org/xpl/conhome/9810327/proceeding
Fitxers | Descripció | Mida | Format | Visualitza |
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S5-1.pdf | 1,186Mb | Accés restringit |