S4 - Machine learning based soft error rate estimation of pass transistor logic in high-speed communication
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hdl:2117/372146
Tipus de documentText en actes de congrés
Data publicació2022-05
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Abstract
Recent advanced high-speed communication systems,
such as optical systems, require highest reliability at lowest
possible power consumption. Thus, Pass Transistor Logic (PTL)
is gaining lots of interest in these communication systems due
to its power saving potential compared to traditional CMOS
logic. However, due to the non-conventional logic structure, its
susceptibility to radiation-induced soft errors is different from
CMOS circuitry. Due to the unique generation and propagation
of Single Event Transients (SETs) in PTL, different approaches
for PTL soft error rate (SER) estimation are required. In
this paper we propose a machine learning (ML) approach for
SET propagation in PTL logic. Multi-layer feed-forward neural
network together with support vector classifier (SVC) are used to
build the SET pulse width and pulse amplitude models. Bayesian
optimization using Gaussian Processes is utilized to tune the
hyperparameters of neural network. The experimental results on
full adder (FA), which is the key component in many large cirucits
such as ALU, and comparison with Monte Carlo (MC) spectre
simulations confirm the accuracy and speed of the proposed
method.
CitacióZhang, Z. [et al.]. S4 - Machine learning based soft error rate estimation of pass transistor logic in high-speed communication. A: 27th IEEE European Test Symposium (ETS). 2022,
Versió de l'editorhttps://ieeexplore.ieee.org/xpl/conhome/9810327/proceeding
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