S3 - On Extracting Reliability Information from Speed Binning
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Document typeConference report
Defense date2022-05
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Abstract
Adaptive Voltage Frequency Scaling (AVFS) is an
important means to overcome process-induced variability challenges
for advanced high-performance circuits. AVFS requires
and allows determining the maximum speed Fmax(Vdd) reachable
under a set of certain operation voltages Vdd. In this paper, it is
shown that the Fmax(Vdd) measurements contain relevant data
to identify some hidden defects in a chip which are reliability
threats and can cause device failures, but pass the speed binning
procedure within the given specifications.
Static Timing Analysis (STA) is applied to a circuit designed by
using standard cell libraries in which the underlying transistors
along with process variations have been carefully calibrated
against industrial 14nm FinFET measurement data, and instances
with and without injected small resistive open defects are
generated. From the slope of the function Fmax(Vdd), a machine
learning procedure can identify some defects with high precision
and few false positives. These chips can be then discarded
without any further need and cost for testing. It has to be noted
that this reliability information comes for free from the data
which is already generated, and does not need any additional
measurements.
CitationNajafi-Haghi, Z.P. [et al.]. S3 - On Extracting Reliability Information from Speed Binning. A: 27th IEEE European Test Symposium (ETS). 2022,
Publisher versionhttps://ieeexplore.ieee.org/xpl/conhome/9810327/proceeding
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