POS2 - Concurrent Error Detection for LSTM Accelerators
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Document typeConference report
Defense date2022-05
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Abstract
The widespread usage of Long Short-Term Memory
(LSTM) accelerators in time-series related applications
necessitates using a protection mechanism against faults caused by
wear-out and environmental effects. This paper proposes a
Concurrent Error Detection (CED) scheme combining low
overhead duplication and residue codes to detect faults in multiply
and add stages of LSTM accelerators. For the multiply stage, the
CED consists of a multiplier for every LSTM multiplier with a
temporal selection of data. For the add stage, the CED adders are
shared among the LSTM adders, thus spatial selection is
performed. The experimental results show that the proposed
method yields good detection probability with a lower area and
power overhead in comparison with the traditional duplication
techniques that indiscriminately duplicate all hardware structures
all the time.
CitationNosrati, N. [et al.]. POS2 - Concurrent Error Detection for LSTM Accelerators. A: 27th IEEE European Test Symposium (ETS). 2022,
Publisher versionhttps://ieeexplore.ieee.org/xpl/conhome/9810327/proceeding
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