Memory requirements are constantly increasing in
System on Chip (SoC) devices. To keep on with this demand,
manufacturers rely on embedded Flash memories that are easily
scalable and relatively cheap to manufacture. These memories
usually take a large percentage of the die area, and their reliability
and verification process are thus two of the critical factors for
a high yield. The testing efforts ensure that each commercialized
device is compliant with the provided specifications but has to
deal with a set of faults specific to embedded flash memories.
Tests must span from pure analogic power measurements to
individual cell-by-cell functionality checks. For the latter, Built
In Self Test (BIST) is the most efficient solution given its orders
of magnitude reduction in test time (compared to CPU-controlled
tests), with a minimal cost due to the increased circuit complexity
and die area. Given the regular structure of flash memories,
BISTs are easily implemented and replicated multiple times.
Such testing solutions allow the verification of all the banks in
parallel, further increasing the advantages of the BIST. Carefully
organizing both hardware and software components of the BISTs
may lead to a significant reduction in test time without affecting
the final test quality. Looking at it from another perspective,
the BISTs may generate a considerable amount of diagnostic
data during the tests. Efficiently collecting this data is crucial
for designers and test engineers who can improve the production
process or strengthen their design. An intelligent solution for this
task is an on-chip method to compact diagnostic information
during embedded memory testing. This strategy permits the
reconstruction of failure bitmaps without any loss. The proposed
method uses a fraction of the memory requested by a coordinatebased
bit mapping approach. At the cost of a moderate test
time overhead, this strategy permits dramatically increasing the
number of devices that can be fully diagnosed without any bitmap
reconstruction loss.
