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De-RISC: A complete RISC-V based space-grade platform
dc.contributor.author | Wessman, Nils-Johan |
dc.contributor.author | Malatesta, Fabio |
dc.contributor.author | Ribes, Stefano |
dc.contributor.author | Andersson, Jan |
dc.contributor.author | García Vilanova, Antonio |
dc.contributor.author | Masmano Tello, Miguel |
dc.contributor.author | Nicolau Gallego, Vicente |
dc.contributor.author | Gómez Molinero, Paco |
dc.contributor.author | Le Rhun, Jimmy |
dc.contributor.author | Alcaide Portet, Sergi |
dc.contributor.author | Cabo Pitarch, Guillem |
dc.contributor.author | Bas Jalón, Francisco |
dc.contributor.author | Benedicte Illescas, Pedro |
dc.contributor.author | Mazzocchetti, Fabio |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.other | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2022-06-02T06:27:56Z |
dc.date.available | 2022-06-02T06:27:56Z |
dc.date.issued | 2022 |
dc.identifier.citation | Wessman, N. [et al.]. De-RISC: A complete RISC-V based space-grade platform. A: Design, Automation and Test in Europe Conference and Exhibition. "Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE 2022): 14-23 March 2022, online virtual platform". Institute of Electrical and Electronics Engineers (IEEE), 2022, p. 802-807. ISBN 978-3-9819263-6-1. DOI 10.23919/DATE54114.2022.9774557. |
dc.identifier.isbn | 978-3-9819263-6-1 |
dc.identifier.uri | http://hdl.handle.net/2117/367939 |
dc.description.abstract | The H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and basic multicore space-grade processors in the market; (2) access to an increasingly rich software ecosystem rather than sticking to the slowly fading SPARC and PowerPC-based ones; (3) freedom (or drastic reduction) of export and license restrictions imposed by commercial ISAs such as Arm; and (4) improved support for the design and validation of safety-related real-time applications, (5) being the platform with software qualified and hardware designed per established space industry standards. De-RISC partners have set up the different layers of the platform during the first phases of the project. However, they have recently boosted integration and assessment activities. This paper introduces the De-RISC space platform, presents recent progress such as enabling virtualization and software qualification, new MPSoC features, and use case deployment and evaluation, including a comparison against other commercial platforms. Finally, this paper introduces the ongoing activities that will lead to the hardware and fully qualified software platform at TRL8 on FPGA by September 2022. |
dc.description.sponsorship | This project has received funding from the European Union’s Horizon 2020 Research and Innovation programme under Grant Agreement EIC-FTI 869945. BSC work has also been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-07255GBC21/AEI/10.13039/501100011033. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Real-time data processing |
dc.subject.lcsh | Multiprocessors |
dc.subject.lcsh | Embedded computer systems |
dc.subject.other | Industries |
dc.subject.other | Program processors |
dc.subject.other | Multicore processing |
dc.subject.other | Licenses |
dc.subject.other | Software |
dc.subject.other | Hardware |
dc.title | De-RISC: A complete RISC-V based space-grade platform |
dc.type | Conference report |
dc.subject.lemac | Temps real (Informàtica) |
dc.subject.lemac | Multiprocessadors |
dc.subject.lemac | Ordinadors immersos, Sistemes d' |
dc.identifier.doi | 10.23919/DATE54114.2022.9774557 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/9774557 |
dc.rights.access | Open Access |
local.identifier.drac | 33759634 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-107255GB-C21/ES/BSC - COMPUTACION DE ALTAS PRESTACIONES VIII/ |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/H2020/869945/EU/De-RISC: Dependable Real-time Infrastructure for Safety-critical Computer/De-RISC |
local.citation.author | Wessman, N.; Malatesta, F.; Ribes, S.; Andersson, J.; García, A.; Masmano, M.; Nicolau, V.; Gómez, P.; Le Rhun, J.; Alcaide, S.; Cabo, G.; Bas, F.; Benedicte, P.; Mazzocchetti, F.; Abella, J. |
local.citation.contributor | Design, Automation and Test in Europe Conference and Exhibition |
local.citation.publicationName | Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE 2022): 14-23 March 2022, online virtual platform |
local.citation.startingPage | 802 |
local.citation.endingPage | 807 |