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De-RISC: A complete RISC-V based space-grade platform

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10.23919/DATE54114.2022.9774557
 
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Wessman, Nils-Johan
Malatesta, Fabio
Ribes, Stefano
Andersson, Jan
García Vilanova, Antonio
Masmano Tello, Miguel
Nicolau Gallego, Vicente
Gómez Molinero, Paco
Le Rhun, Jimmy
Alcaide Portet, SergiMés informacióMés informació
Cabo Pitarch, Guillem
Bas Jalón, Francisco
Benedicte Illescas, PedroMés informació
Mazzocchetti, Fabio
Abella Ferrer, JaumeMés informació
Document typeConference report
Defense date2022
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
ProjectBSC - COMPUTACION DE ALTAS PRESTACIONES VIII (AEI-PID2019-107255GB-C21)
De-RISC - De-RISC: Dependable Real-time Infrastructure for Safety-critical Computer (EC-H2020-869945)
Abstract
The H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and basic multicore space-grade processors in the market; (2) access to an increasingly rich software ecosystem rather than sticking to the slowly fading SPARC and PowerPC-based ones; (3) freedom (or drastic reduction) of export and license restrictions imposed by commercial ISAs such as Arm; and (4) improved support for the design and validation of safety-related real-time applications, (5) being the platform with software qualified and hardware designed per established space industry standards. De-RISC partners have set up the different layers of the platform during the first phases of the project. However, they have recently boosted integration and assessment activities. This paper introduces the De-RISC space platform, presents recent progress such as enabling virtualization and software qualification, new MPSoC features, and use case deployment and evaluation, including a comparison against other commercial platforms. Finally, this paper introduces the ongoing activities that will lead to the hardware and fully qualified software platform at TRL8 on FPGA by September 2022.
CitationWessman, N. [et al.]. De-RISC: A complete RISC-V based space-grade platform. A: Design, Automation and Test in Europe Conference and Exhibition. "Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE 2022): 14-23 March 2022, online virtual platform". Institute of Electrical and Electronics Engineers (IEEE), 2022, p. 802-807. ISBN 978-3-9819263-6-1. DOI 10.23919/DATE54114.2022.9774557. 
URIhttp://hdl.handle.net/2117/367939
DOI10.23919/DATE54114.2022.9774557
ISBN978-3-9819263-6-1
Publisher versionhttps://ieeexplore.ieee.org/document/9774557
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  • Doctorat en Arquitectura de Computadors - Ponències/Comunicacions de congressos [232]
  • Computer Sciences - Ponències/Comunicacions de congressos [500]
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