CMOS inverter performance degradation and its correlation with BTI, HCI and OFF state MOSFETs aging

Abstract

In this work, CMOS inverters are subjected to electrical stress emulating a complete operation cycle and the shifts in the performance parameters (i.e., peak current and inversion voltage) evaluated. Moreover, degradation of the two MOSFETs is also measured as variations of their threshold voltage and mobility. The relationships between the observed transistors and circuit parameter shifts are explained in terms of the different device aging mechanisms (i.e., BTI, CHI and OFF-state) that are active depending on the voltages at the circuit terminals. Moreover, the combined effects of the aging mechanisms that are sequentially activated, at device and circuit levels, and their voltage dependence, are also discussed. Finally, a power law fitting of the inversion voltage degradation of the inverter is used to evaluate its variation at operating conditions.