An FPGA accelerator of the wavefront algorithm for genomics pairwise alignment
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hdl:2117/366104
Document typeConference report
Defense date2021
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
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ProjectHiPEAC - High Performance Embedded Architecture and Compilation (EC-H2020-871174)
UPC-COMPUTACION DE ALTAS PRESTACIONES VIII (AEI-PID2019-107255GB-C22)
UPC-COMPUTACION DE ALTAS PRESTACIONES VIII (AEI-PID2019-107255GB-C22)
Abstract
In the last years, advances in next-generation sequencing technologies have enabled the proliferation of genomic applications that guide personalized medicine. These applications have an enormous computational cost due to the large amount of genomic data they process. The first step in many of these applications consists in aligning reads against a reference genome. Very recently, the wavefront alignment algorithm has been introduced, significantly reducing the execution time of the read alignment process. This paper presents the first FPGA- based hardware/software co-designed accelerator of such relevant algorithm. Compared to the reference WFA CPU-only implementation, the proposed FPGA accelerator achieves performance speedups of up to 13.5× while consuming up to 14.6× less energy.ed medicine. These applications have an enormous computational cost due to the large amount of genomic data they process. The first step in many of these applications consists in aligning reads against a reference genome. Very recently, the wavefront alignment algorithm has been introduced, significantly reducing the execution time of the read alignment process. This paper presents the first FPGA- based hardware/software co-designed accelerator of such relevant algorithm. Compared to the reference WFA CPU-only imple- mentation, the proposed FPGA accelerator achieves performance speedups of up to 13.5× while consuming up to 14.6× less energy.
CitationHaghi, A. [et al.]. An FPGA accelerator of the wavefront algorithm for genomics pairwise alignment. A: International Conference on Field-Programmable Logic and Applications. "2021 31st International Conference on Field-Programmable Logic and Applications, FPL 2021: Dresden, Germany, 30 August–3 September 2021: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2021, p. 151-159. ISBN 978-1-6654-3759-2. DOI 10.1109/FPL53798.2021.00033.
ISBN978-1-6654-3759-2
Publisher versionhttps://ieeexplore.ieee.org/document/9556445
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