A low-power hardware accelerator for ORB feature extraction in self-driving cars
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hdl:2117/361565
Document typeConference report
Defense date2021
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
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ProjectCoCoUnit - CoCoUnit: An Energy-Efficient Processing Unit for Cognitive Computing (EC-H2020-833057)
ARQUITECTURAS DE DOMINIO ESPECIFICO PARA SISTEMAS DE COMPUTACION ENERGETICAMENTE EFICIENTES (AEI-PID2020-113172RB-I00)
ARQUITECTURAS DE DOMINIO ESPECIFICO PARA SISTEMAS DE COMPUTACION ENERGETICAMENTE EFICIENTES (AEI-PID2020-113172RB-I00)
Abstract
Simultaneous Localization And Mapping (SLAM) is a key component for autonomous navigation. SLAM consists of building and creating a map of an unknown environment while keeping track of the exploring agent's location within it. An effective implementation of SLAM presents important challenges due to real-time inherent constraints and energy consumption. ORB-SLAM is a state-of-the-art Visual SLAM system based on cameras that can be used for self-driving cars. In this paper, we propose a high-performance, energy-efficient and functionally accurate hardware accelerator for ORB-SLAM, focusing on its most time-consuming stage: Oriented FAST and Rotated BRIEF (ORB) feature extraction. We identify the BRIEF descriptor generation as the main bottleneck, as it exhibits highly irregular access patterns to local on-chip memories, causing a high performance penalty due to bank conflicts. We propose a genetic algorithm to generate an optimal memory access pattern offline, which greatly simplifies the hardware while minimizing bank conflicts in the computation of the BRIEF descriptor. Compared with a CPU system, the accelerator achieves 8x speedup and 1957x reduction in power dissipation.
CitationTaranco, R.; Arnau, J.; González, A. A low-power hardware accelerator for ORB feature extraction in self-driving cars. A: International Symposium on Computer Architecture and High Performance Computing. "2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2021: 26–29 October 2021, virtual event: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2021, p. 11-21. ISBN 978-1-6654-4301-2. DOI 10.1109/SBAC-PAD53543.2021.00013.
ISBN978-1-6654-4301-2
Publisher versionhttps://ieeexplore.ieee.org/document/9651662
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