Analysis of asynchronous routers for network-on-chip applications
Estadístiques de LA Referencia / Recolecta
Inclou dades d'ús des de 2022
Cita com:
hdl:2117/359869
Tipus de documentTreball Final de Grau
Data2019-07-12
Condicions d'accésAccés obert
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Abstract
Asynchronous circuit design has been conventionally regarded as a valid alternative to synchronous logic due to its potential for low consumption of resources, power and delay. This includes areas such as the communication infrastructure of modern multi core processors, the so-called Network-on-Chip (NoC) paradigm on which this thesis focus on. In recent times, the transistor downscaling and the increasing clock frequencies have pushed synchronous design to high static power and delay. As a result, the interest for asynchronous integrated routers and links has re-emerged, especially in fields with ultra-low power requirements such as embedded systems. In this thesis, we construct an asynchronous router using Verilog code based on architectures found in the literature. We analyze the functionality of each of the building blocks and verify the operation of the implemented routing algorithm and arbitration mechanism. In the future, the results obtained here are expected to enable a complete implementation of the router in Verilog and its posterior analysis of its scalability.
TitulacióMOBILITAT INCOMING
Fitxers | Descripció | Mida | Format | Visualitza |
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Bachelor Thesis Roshni.pdf | 1,294Mb | Visualitza/Obre | ||
code-Bachelor Thesis.zip | 6,264Kb | application/zip | Visualitza/Obre |