PrioRAT: criticality-driven prioritization inside the on-chip memory hierarchy
Visualitza/Obre
10.1007/978-3-030-85665-6_37
Inclou dades d'ús des de 2022
Cita com:
hdl:2117/356625
Tipus de documentText en actes de congrés
Data publicació2021
EditorSpringer Nature
Condicions d'accésAccés obert
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Abstract
The ever-increasing gap between the processor and main memory speeds requires careful utilization of the limited memory link. This is additionally emphasized for the case of memory-bound applications. Prioritization of memory requests in the memory controller is one of the approaches to improve performance of such codes. However, current designs do not consider high-level information about parallel applications. In this paper, we propose a holistic approach to this problem, where the runtime system-level knowledge is made available in hardware. Processor exploits this information to better prioritize memory requests, while introducing negligible hardware cost. Our design is based on the notion of critical path in the execution of a parallel code. The critical tasks are accelerated by prioritizing their memory requests within the on-chip memory hierarchy. As a result, we reduce the critical path and improve the overall performance up to 1.19× compared to the baseline systems.
CitacióDimić, V. [et al.]. PrioRAT: criticality-driven prioritization inside the on-chip memory hierarchy. A: International European Conference on Parallel and Distributed Computing. "Euro-Par 2021: Parallel Processing 27th International Conference on Parallel and Distributed Computing: Lisbon, Portugal, September 1–3, 2021: proceedings". Springer Nature, 2021, p. 599-615. ISBN 978-3-030-85665-6. DOI 10.1007/978-3-030-85665-6_37.
ISBN978-3-030-85665-6
Versió de l'editorhttps://link.springer.com/chapter/10.1007%2F978-3-030-85665-6_37
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